Transistors, such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs), are the core building blocks of the vast majority of semiconductor integrated circuits (ICs). A FET includes source and drain regions between which a current can flow through a channel under the influence of a bias applied to a gate electrode that overlies the channel. A fin field effect transistor (FinFET) is a type of transistor that lends itself to the dual goals of reducing transistor size while maintaining transistor performance. The FinFET is a three dimensional transistor formed with a thin fin that extends upwardly from a semiconductor substrate. In a FinFET, the transistor channel is formed along the vertical sidewalls of the fin, so a wide channel, and hence a very efficient layout, can be achieved without substantially increasing the area of the substrate surface required by the transistor.
Traditional FinFETs are produced from monocrystalline silicon. However, transistor performance or functionality can be significantly increased by forming fins from other materials, such as silicon-germanium (SiGe), germanium, or from compounds including elements from Groups III and/or V of the Periodic Table, (sometimes referred to as “III-V materials,” “3-5 materials,” or “III/V fins”). Such materials provide higher carrier velocity and higher drive currents at a given bias than comparable silicon materials. These materials may also enable additional functionality as a result of the materials properties, such as the presence of a direct bandgap. These other materials can be epitaxially grown from a base silicon crystal, but the presence of silicon oxide on the surface of the silicon crystal interferes with the epitaxial growth. Silicon oxide forms rapidly when silicon is exposed to the atmosphere, so a precleaning process is used to eliminate silicon oxide before epitaxially growth.
Epitaxially grown replacement fins have been produced by forming shallow trench isolation regions between “dummy” fins, removing the “dummy” fins to leave a void between the shallow trench isolation regions, and epitaxially growing the replacement fin in the void. Traditionally, the shallow trench isolation regions are primarily formed of silicon oxide. The dimensions of the void and the replacement fin, especially the width between adjacent shallow trench isolation regions, are important in determining the electrical properties of the final FinFET. However, the precleaning process that removes silicon oxide from the crystalline silicon also removes silicon oxide from the shallow trench isolation regions. The removal of silicon oxide increases the dimensions of the void where the replacement fin will be grown, so the dimensions of the replacement fin are larger than the designed dimensions based on the size and location of the shallow trench isolation regions. Silicon oxide may also be removed at varying rates in the precleaning process, which further complicates matters, because the dimension of the resulting fins vary from one fin to the next.
Accordingly, it is desirable to provide a replacement fin with dimensions that match the size and shape of the void produced by adjacent shallow trench isolation regions, and methods for producing the same. In addition, it is desirable to provide other replacement structures, such as components of planar FETs or interconnects, with consistently sized shallow trench isolation regions and methods for producing such replacement structures. Furthermore, other desirable features and characteristics of the present embodiment will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.